Yaseen Salah

@yaseensalah

Digital ASIC/FPGA Design and Verification Engineer.

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Language Breakdown

Lines of code distribution across 4 owned repositories

192K Total LOC

Verilog

106,324 lines

55.3%

N/A

CSS

47,681 lines

24.8%

N/A

HTML

38,073 lines

19.8%

N/A

JavaScript

131 lines

0.1%

N/A

T-Shaped Developer

T-shaped

Deep in Verilog with broad versatility

Verilog

CSS

HTML

JavaScript

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+18%

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Coding Streak

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Followers 30

lwenxi65-glitch

@lwenxi65-glitch

Rohan Dey

@rohan1o

Sherif Shawky

@Sherifshawky123

krushnamshah

@krushnamshah

Samet Akın

@sametakinn

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Following

3 total

Mohamed Tarek

@mohamedtareq24

Nour Eldeen Samir

@nour176yj

Ahmed Abdelazeem

@abdelazeem201

Synced via GitHub

Top Repositories

Digital-Design-of-FIR-Filter

Hardware Design and Verification of a configurable and parametrized 50th order low-pass FIR filter starting from MATLAB Modeling to Verilog RTL Design and Simulink Testing with .wav audio files.

31 6

Verilog

32-bit-Single-Cycle-RISC-V

Digital Design and Verification of 32-bit Single Cycle RISC-V Processor using Verilog HDL and Xilinx Vivado

7 2

Verilog

ASIC-Design-of-Low-Power-Configurable-Multi-Clock-Digital-System-With-UART-Transceiver

RTL to GDS|| Implementation of a Digital System supporting Read, Write, Low-Power ALU Operation With/Without Operand Commands through core blocks operation with 50 MHz interfaced with 6.9 KHz UART peripheral.

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